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參數(shù)資料
| 型號： | MSC7110VF800 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | FLUORESCENT DSPL CTRL, PBGA400 |
| 封裝： | 17 X 17 MM, BGA-400 |
| 文件頁數(shù)： | 42/56頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MSC7110VF800 |
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Hardware Design Considerations
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
47
3.3.2
Peripheral Power
Peripherals include the DDR memory controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the I
2C module.
Basic power consumption by each module is assumed to be the same and is computed by using the following equation which
assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100 MH or 133 MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)
2 × 100 MHz × 10–3 = 2.88 mW per peripheral
Eqn. 7
PPERIPHERAL = 20 pF × (1.2 V)
2
× 133 MHz × 10–3 = 3.83 mW per peripheral
Eqn. 8
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7110
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC
Eqn. 9
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V
Eqn. 10
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)
2
× 200 MHz × 10–3 mW
Eqn. 11
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)
2
× 266 MHz × 10–3 mW
Eqn. 12
pin activity value = (active data lines
× % activity × % data switching) + (active address lines × % activity)
Eqn. 13
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
2 × 200 × 10–3) = 324.2 mW
Eqn. 14
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
2
× 266 × 10–3) = 326.3 mW
Eqn. 15
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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