參數(shù)資料
型號(hào): MSC7110
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Low-Cost 16-Bit DSP with DDR Controller
中文描述: 低成本16位數(shù)字信號(hào)處理器與DDR控制器
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 97K
代理商: MSC7110
Freescale Semiconductor
Product Brief
MSC7110PB
Rev. 2, 12/2005
Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
MSC7110
Low-Cost 16-Bit DSP with DDR Controller
The MSC7110 device is a highly integrated DSP processor that contains the StarCore SC1400 core, 64 KB of
SRAM memory, a 16 KB ICache, an 8 KB boot ROM, a 128-channel time-division multiplexing (TDM) interface
with hardware support for
μ
/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host
interface (HDI16) to support an external host processor, a programmable interrupt controller (PIC), an I
2
C
interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and event port for
enhanced debug capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply
accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V.
Figure 1.
MSC7110 Block Diagram
Boot ROM
(8 KB)
RS-232
APB
A
64
UART
External
Memory
Interface
Interrupts
Interrupt
Control
HDI16
Port
32
Host
Interface
(HDI16)
External Bus
Timers
TDM
DSP
Extended
Core
DMA
(32 ch)
Note: The arrows show the direction of the transfer.
64
32
128
32
SC1400
Core
Cache
(16 KB)
Extended
Core
Interface
Unit
Fetch
M1
SRAM
(64 KB)
64
64
128
64
A
TDM
P XA XB
128
64
64
PLL/Clock
PLL/Clock
M
O
Trace
Buffer
(8 KB)
to/from OCE
I
32
Events
32
IPBus
to DMA
to EMI
JTAG
JTAG Port
AMDMA
AMIC
AMEC
ASM1
ASM2
ASEMI
ASTH
ASAPB
from
IPBus
I
2
C
I
2
C
ASSB
GPIO
GPIO
Instruction
to IPBus
Watchdog
Event Port
to Crossbar
System Control
32
ASAPB
The MSC7110 device
targets high-bandwidth
highly computational
DSP applications and
is optimized for
Enterprise class packet
telephony applications,
providing a competitive
price per channel for
voice over packet
systems.
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