參數(shù)資料
型號(hào): MSC1213Y3PAGT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 95/111頁(yè)
文件大小: 1102K
代理商: MSC1213Y3PAGT
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
84
Serial Port 1 Control (SCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR C0h
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00h
SM02
Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in
bits 75
addition to the 8 or 9 data bits.
MODE
SM0
SM1
SM2
FUNCTION
LENGTH
PERIOD
0
Synchronous
8 bits
12 pCLK(1)
0
1
Synchronous
8 bits
4 pCLK(1)
1(2)
0
1
0
Asynchronous
10 bits
Timer 1 Baud Rate Equation
1(2)
0
1
Valid Stop Required(3)
10 bits
Timer 1 Baud Rate Equation
2
1
0
Asynchronous
11 bits
64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
2
1
0
1
Asynchronous with Multiprocessor Communication(4)
11 bits
64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
3(2)
1
0
Asynchronous
11 bits
Timer 1 Baud Rate Equation
3(2)
1
Asynchronous with Multiprocessor Communication(4)
11 bits
Timer 1 Baud Rate Equation
(1) pCLK will be equal to tCLK, except that pCLK will stop for Idle mode.
(2) For modes 1 and 3, the selection of Timer 1 for baud rate is specified via the T2CON (C8h) register.
(3) RI_0 will only be activated when a valid STOP is received.
(4) RI_0 will not be activated if bit 9 = 0.
REN_1
Receive Enable. This bit enables/disables the serial Port 1 received shift register.
bit 4
0 = Serial Port 1 reception disabled.
1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_1
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3.
bit 3
RB8_1
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes
bit 2
2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0.
TI_1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out.
bit 1
In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last
data bit. This bit must be cleared by software to transmit the next byte.
RI_1
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial
bit 0
port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming
stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must
be cleared by software to receive the next byte.
Serial Data Buffer 1 (SBUF1)
7
6
5
4
3
2
1
0
Reset Value
SFR C1h
00h
SBUF1.70 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive
bits 70
buffers are separate registers, but both are addressed at this location.
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