參數(shù)資料
型號(hào): MSC1212Y3PAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 70/111頁(yè)
文件大?。?/td> 1113K
代理商: MSC1212Y3PAGR
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
61
I2C Status (I2CSTAT) (Available only on the MSC1211 and MSC1213)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Dh
STAT7
SCKD7/SAE
STAT6
SCKD6/SA6
STAT5
SCKD5/SA5
STAT4
SCKD4/SA4
STAT3
SCKD3/SA3
0
SCKD2/SA2
0
SCKD1/SA1
0
SCKD0/SA0
00h
STAT73
Status Code. Read-only. Reading this register clears the status interrupt.
bit 73
STATUS CODE
STATUS OF THE HARDWARE
MODE
0x08
START condition transmitted.
Master
0x10
Repeated START condition transmitted.
Master
0x18
Slave address + W transmitted and ACK received.
Master
0x20
Slave address + W transmitted and NACK received.
Master
0x28
Data byte transmitted and ACK received.
Master
0x30
Data byte transmitted and NACK received.
Master
0x38
Arbitration lost.
Master
0x40
Slave address + R transmitted and ACK received.
Master
0x48
Slave address + R transmitted and NACK received.
Master
0x50
Data byte received and ACK transmitted.
Master
0x58
Data byte received and NACK transmitted.
Master
0x60
I2Cs slave address + W received and ACK transmitted.
Slave
0x70
General call received and ACK transmitted.
Slave
0x80
Previously addressed as slave, data byte received and ACK transmitted.
Slave
0x88
Previously addressed as slave, data byte received and NACK transmitted.
Slave
0x90
Previously addressed with GC, data byte received and ACK transmitted.
Slave
0x98
Previously addressed with GC, data byte received and NACK transmitted.
Slave
0xA0
A STOP or repeated START received when addressed as slave or GC.
Slave
0xA8
I2Cs slave address + R received and ACK transmitted.
Slave
0xB8
Previously addressed as slave, data byte transmitted and ACK received.
Slave
0xC0
Previously addressed as slave, data byte transmitted and NACK received.
Slave
0xC8
Previously addressed as slave, last data byte transmitted.
Slave
SCKD70
Serial Clock Divisor. Write-only, master mode.
bit 70
The frequency of the SCL line is set equal to Sysclk/[2
(SCKD + 1)]. The minimum value for SCKD is 3.
SAE
Slave Address Enable. Write-only, slave mode.
bit 7
In slave mode, if this is set, address recognition is enabled.
SA60
Slave Address. Write-only, slave mode.
bit 60
The address of this device is used in slave mode for address recognition.
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