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參數(shù)資料
| 型號(hào)： | MS80C51T-20R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
| 文件頁(yè)數(shù)： | 122/170頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | MS80C51T-20R |
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55
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
11.3.2
External Clock Source
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
Tn). The Tn pin is sampled
once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed
through the edge detector. Figure 11-3 on page 55 shows a functional equivalent block diagram of the T0 synchro-
nization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clk
I/O).
The latch is transparent in the high period of the internal system clock.
The edge detector generates one clk
T0 pulse for each positive (CS2:0 = 7) or negative (CS2:0 = 6) edge it detects.
Figure 11-3.
T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam-
pling. The external clock must be guaranteed to have less than half the system clock frequency (f
ExtClk < fclk_I/O/2)
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is rec-
ommended that maximum frequency of an external clock source is less than f
clk_I/O/2.5.
An external clock source can not be prescaled.
11.4
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 11-4 on
page 55 shows a block diagram of the counter and its surroundings.
Figure 11-4.
Counter Unit Block Diagram
Signal description (internal signals):
Tn_sync
(To Clock
Select Logic)
Edge Detector
Synchronization
DQ
LE
DQ
Tn
clk
I/O
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP
BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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