參數(shù)資料
型號: MS32
廠商: Texas Instruments, Inc.
英文描述: QUADRUPLE 2-INPUT POSITIVE-OR GATE
中文描述: 四2輸入的正或門
文件頁數(shù): 1/9頁
文件大小: 410K
代理商: MS32
www.ti.com
FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t
pd
of 2.2 ns at 1.8 V
Low Power Consumption, 10-
μ
A Max I
CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
4B
4A
4Y
3B
3A
1B
1Y
2A
2B
2Y
1
3
V
G
C
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-OR gate is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for
1.65-V to 1.95-V V
CC
operation.
The SN74AUC32 device performs the Boolean function
Y
A
B or Y
A
B
in positive logic.
A
B
Y
SN74AUC32
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCES513A–NOVEMBER 2003–REVISED MARCH 2005
This device is fully specified for partial-power-down applications using I
. The I
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
Tape and reel
ORDERABLE PART NUMBER
SN74AUC32RGYR
TOP-SIDE MARKING
MS32
–40°C to 85°C
QFN – RGY
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
H
X
L
B
X
H
L
H
H
L
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2003–2005, Texas Instruments Incorporated
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