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| 型號(hào)： | MR83C154TXXX-20/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 6/232頁(yè) |
| 文件大?。?/td> | 61013K |
| 代理商： | MR83C154TXXX-20/883 |
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103
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare
MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs.
The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow inter-
rupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs.
The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
13.3.7
TIFR – Timer/Counter Interrupt Flag Register
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A -
Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When
the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed.
Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle,
by writing a logical one to the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable),
and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
13.3.8
PLLCSR – PLL Control and Status Register
Bits 6:3 – Res : Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
Bit 2 – PCKE: PCK Enable
The bit PCKE is always set in the ATtiny15 compatibility mode.
Bit 1 – PLLE: PLL Enable
The PLL is always enabled in the ATtiny15 compatibility mode.
Bit
7
6
5
4
3
2
1
0
–OCF1A
OCF1B
OCF0A
OCF0B
TOV1
TOV0
–
TIFR
Read/Write
R
R/W
R
Initial value
0
Bit
7
6
543
210
LSM
–
PCKE
PLLE
PLOCK
PLLCSR
Read/Write
R/W
R
R/W
R
Initial value
0
0/1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C154-25P883 | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154DXXX-12P883D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MQ83C154DTXXX-20P883 | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| MR83C154DXXX-25/883D | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154UXXX-25:R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
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