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參數(shù)資料
| 型號： | MR83C154CXXX-36/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 317/339頁 |
| 文件大?。?/td> | 5007K |
| 代理商： | MR83C154CXXX-36/883 |
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SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
13.8.4.4 Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and
associated status bits.
Assuming that:
1.
The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service rou-
tine address, and the interrupt source 0 is enabled.
2.
The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:
LDR PC, [PC, # -&F20]
3.
The user does not need nested fast interrupts.
When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is:
1.
The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register
(R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address
0x20, the ARM core adjusts R14_fiq, decrementing it by four.
2.
The ARM core enters FIQ mode.
3.
When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in
AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed
to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.
4.
The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the
link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed.
5.
The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ
mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be
saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is pro-
grammed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert
the interrupt source 0.
6.
Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC,
LR, #4
for example). This has the effect of returning from the interrupt to whatever was being executed before,
loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the
SPSR.
Note:
The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts
when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is com-
pleted (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C.
This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the
handler operation. However, this method saves the execution of a branch instruction.
13.8.4.5 Fast Forcing
The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the
fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing
Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register
(AIC_FFSR) that controls the feature for each internal or external interrupt source.
When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages.
When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source
is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler.
If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the
assertion of the nFIQ line to the core.
If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the
assertion of the nFIQ line to the core.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C52TXXX-36SHXXX:D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| MR80C52TXXX-36SHXXX:D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| MC80C32E-20SC | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C52CXXX-25SBR | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32E-25SBD | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR83C154-L16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR83C154T-12 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR83C154T-16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR83C154T-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR83C154T-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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