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參數(shù)資料
| 型號： | MR80C88/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 5 MHz, MICROPROCESSOR, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 633K |
| 代理商： | MR80C88/B |
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7
Functional Description
Static Operation
All 80C88 circuitry is static in design. Internal registers,
counters and latches are static and require not refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other microproces-
sors. The CMOS 80C88 can operate from DC to the
specified upper frequency limit. The processor clock may be
stopped in either state (high/low) and held there indefinitely.
This type of operation is especially useful for system debug
or power critical applications.
The 80C88 can be single stepped using only the CPU clock.
This state can be maintained as long as is necessary. Single
step clock operation allows simple interface circuitry to
provide critical information for start-up.
Static design also allows very low frequency operation (as
low as DC). In a power critical situation, this can provide
extremely low power operation since 80C88 power dissipa-
tion is directly related to operation frequency. As the system
frequency is reduced, so is the operating power until, at a
DC input frequency, the power requirement is the 80C88
standby current.
Internal Architecture
The internal functions of the 80C88 processor are partitioned
logically into two processing units. The first is the Bus Inter-
face Unit (BIU) and the second is the Execution Unit (EU) as
shown in the CPU block diagram.
These units can interact directly but for the most part
perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic bus
control. The overlap of instruction pre-fetching provided by
this unit serves to increase processor performance through
improved bus bandwidth utilization. Up to 4 bytes of the
instruction stream can be queued while waiting for decoding
and execution.
The instruction stream queuing mechanism allows the BIU to
keep the memory utilized very efficiently. Whenever there is
space for at least 1 byte in the queue, the BIU will attempt a
byte fetch memory cycle. This greatly reduces “dead time”:
on the memory bus. The queue acts as a First-In-First-Out
(FIFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue
immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from the
BIU queue and provides unrelocated operand addresses to
the BIU. Memory operands are passed through the BIU for
processing by the EU, which passes results to the BIU for
storage.
Memory Organization
The processor provides a 20-bit address to memory which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divided into
code, data, extra, and stack segments of up to 64K bytes
each, with each segment falling on 16 byte boundaries. (See
Figure 1).
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of
programs. The segment register to be selected is automati-
cally chosen according to specific rules as shown in Table 1.
All information in one segment type share the same logical
attributes (e.g., code or data). By structuring memory into
relocatable areas of similar characteristics and by automati-
cally selecting segment registers, programs are shorter,
faster, and more structured.
Word (16-bit) operands can be located on even or odd
address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower valued
address location and the most significant byte in the next
higher address location.
TABLE 6.
MEMORY
REFERENCE
NEED
SEGMENT
REGISTER
USED
SEGMENT
SELECTION RULE
Instructions
CODE (CS)
Automatic with all instruction
prefetch.
Stack
STACK (SS)
All stack pushes and pops.
Memory references relative to
BP base register except data
references.
Local Data
DATA (DS)
Data references when: relative
to stack, destination of string op-
eration, or explicitly overridden.
External Data
(Global)
EXTRA (ES)
Destination of string
operations: Explicitly selected
using a segment override.
SEGMENT
REGISTER FILE
CS
SS
DS
ES
64K-BIT
+ OFFSET
FFFFFH
CODE SEGMENT
XXXXOH
STACK SEGMENT
DATA SEGMENT
EXTRA SEGMENT
00000H
FIGURE 14. MEMORY ORGANIZATION
MSB
BYTE
LSB
70
WORD
80C88
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