
84
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB1 and DDB1 settings. It will also be output during reset.
PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source.
T0/XCK0/PCINT8, Bit 0
T0, Timer/Counter0 counter source.
XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock
is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 14-7.
Overriding Signals for Alternate Functions in PB7:PB4.
Signal
name
PB7/SCK/
PCINT15
PB6/MISO/
PCINT14
PB5/MOSI/
PCINT13
PB4/SS/OC0B/
PCINT12
PUOE
SPE MSTR
PUOV
PORTB7 PUD
PORTB14 PUD
PORTB13 PUD
PORTB12 PUD
DDOE
SPE MSTR
DDOV
0
PVOE
SPE MSTR
OC0A ENABLE
PVOV
SCK OUTPUT
SPI SLAVE
OUTPUT
SPI MSTR OUTPUT
OC0A
DIEOE
PCINT15 PCIE1
PCINT14 PCIE1
PCINT13 PCIE1
PCINT12 PCIE1
DIEOV
111
1
DI
SCK INPUT
PCINT17 INPUT
SPI MSTR INPUT
PCINT14 INPUT
SPI SLAVE INPUT
PCINT13 INPUT
SPI SS
PCINT12 INPUT
AIO
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