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| 型號(hào)： | MR80C52TXXX-36SHXXX:D |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 320/339頁(yè) |
| 文件大?。?/td> | 5007K |
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81
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
1.
Calculates active interrupt (higher than current or spurious).
2.
Determines and returns the vector of the active interrupt.
3.
Memorizes the interrupt.
4.
Pushes the current priority level onto the internal stack.
5.
Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4
and 5 are only performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without
modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.
13.8.6 Spurious Interrupt
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being
the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is
read. This is most prone to occur when:
An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.
An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded
peripheral is activated for a short time. (As in the case for the Watchdog.)
An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt
source.
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When
this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The
programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as
fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from
interrupt.
13.8.7 General Interrupt Mask
The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the
nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this
mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the
processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle
an interrupt. It is strongly recommended to use this mask with caution.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC80C32E-20SC | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C52CXXX-25SBR | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32E-25SBD | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| MR80C154-12P883R | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| MQ83C154TXXX-12P883R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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