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參數(shù)資料
| 型號： | MR80C52TXXX-36SHXXX:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 315/339頁 |
| 文件大?。?/td> | 5007K |
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SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-
asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service
routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an
embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and
the AIC_EOICR is written.
The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to
having eight priority levels.
13.8.3.3 Interrupt Vectoring
The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to
AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value
written into AIC_SVR corresponding to the current interrupt is returned.
This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as
AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address
0x0000 0018 through the following instruction:
LDR
PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching
the execution on the correct interrupt handler.
This feature is often not used when the application is based on an operating system (either real time or not). Operating
systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the
interrupt.
However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt
vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating
system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer
the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This
facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be
handled efficiently and independently of the application running under an operating system.
13.8.3.4 Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the
associated status bits.
It is assumed that:
1.
The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding inter-
rupt service routine addresses and interrupts are enabled.
2.
The instruction at the ARM interrupt exception vector address is required to work with the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1.
The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register
(R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C,
the ARM core adjusts R14_irq, decrementing it by four.
2.
The ARM core enters Interrupt mode, if it has not already done so.
3.
When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in
AIC_IVR. Reading the AIC_IVR has the following effects:
Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level
is the priority level of the current interrupt.
De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to
de-assert nIRQ.
Automatically clears the interrupt, if it has been programmed to be edge-triggered.
相關(guān)PDF資料 |
PDF描述 |
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| MR80C52TXXX-36SHXXX:D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| MC80C32E-20SC | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C52CXXX-25SBR | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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