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| 型號(hào)： | MR80C52TXXX-20/883D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 332/416頁(yè) |
| 文件大?。?/td> | 10516K |
| 代理商： | MR80C52TXXX-20/883D |
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432
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
30.4 Initialization Sequence
The addresses given are for example purposes only. The real address depends on implementation in the product.
30.4.1 SDR-SDRAM Initialization
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence:
1.
Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 468).
2.
Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)),
and into the Configuration Register (number of columns, rows, banks, cas latency) (see Section 30.7.3 on page
3.
For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self
refresh (PASR) must be set in the Low-power Register (see Section 30.7.7 on page 466).
A minimum pause of 200 s is provided to precede any signal toggle.
4.
A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must
set Mode to 1 in the Mode Register (See Section 30.7.1 on page 457). Perform a write access to any SDR-
SDRAM address to acknowledge this command. Now the clock which drives SDR-SDRAM device is enabled.
5.
An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into
Mode Register, the application must set Mode to 2 in the Mode Register (See Section 30.7.1 on page 457). Per-
form a write access to any SDR-SDRAM address to acknowledge this command.
6.
Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the
application must set Mode to 4 in the Mode Register (see Section 30.7.1 on page 457).Performs a write access to
any SDR-SDRAM location eight times to acknowledge these commands.
7.
A Mode Register set (MRS) cycle is issued to program the parameters of the SDR-SDRAM devices, in particular
CAS latency and burst length. The application must set Mode to 3 in the Mode Register (see Section 30.7.1 on
page 457) and perform a write access to the SDR-SDRAM to acknowledge this command. The write address must
be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM (12 rows, 9 columns, 4
banks) bank address, the SDRAM write access should be done at the address 0x20000000.
Note:
This address is for example purposes only. The real address is dependent on implementation in the product.
8.
For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the
SDR-SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see Sec-
tion 30.7.1 on page 457) and perform a write access to the SDR-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM,
(12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000.
9.
The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see Section 30.7.1 on page
457) and perform a write access at any location in the SDRAM to acknowledge this command.
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see page 458). (Refresh rate =
delay between refresh cycles). The SDR-SDRAM device requires a refresh every 15.625 s or 7.81 s. With a 100
MHz frequency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 i.e. 0x061A or
(7.81*100 MHz) = 781 i.e. 0x030d
After initialization, the SDR-SDRAM device is fully functional.
30.4.2 Low-power DDR1-SDRAM Initialization
The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the
following sequence:
1.
Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 468).
2.
Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous tim-
ing (trc, tras, etc.), number of columns, rows, banks, cas latency. See Section 30.7.3 on page 459, Section 30.7.4
3.
Program temperature compensated self refresh (tcr), Partial array self refresh (pasr) and Drive strength (ds) into
the Low-power Register. See Section 30.7.7 on page 466.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ83C154CXXX-20P883D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32-36/883R | 8-BIT, 36 MHz, MICROCONTROLLER, CQCC44 |
| MR80C154U-36:D | MICROCONTROLLER |
| MR80C52TXXX-30SBD | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52EXXX-36/883D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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