參數(shù)資料
型號(hào)： MR80C52EXXX-25SC
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁(yè)數(shù)： 46/109頁(yè)
文件大?。?/td> 10824K
代理商： MR80C52EXXX-25SC
29
AT32UC3A
9.4
Exceptions and Interrupts
AVR32UC incorporates a powerful exception handling scheme. The different exception sources,
like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-
defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri-
ority class.
When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in Table 9-4 on page 32. Most of the han-
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif-
ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.
An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.
9.4.1
System stack issues
Event handling in AVR32 UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
92
368
MPUPSR4
MPU Privilege Select Register region 4
93
372
MPUPSR5
MPU Privilege Select Register region 5
94
376
MPUPSR6
MPU Privilege Select Register region 6
95
380
MPUPSR7
MPU Privilege Select Register region 7
96
384
MPUCRA
Unused in this version of AVR32UC
97
388
MPUCRB
Unused in this version of AVR32UC
98
392
MPUBRA
Unused in this version of AVR32UC
99
396
MPUBRB
Unused in this version of AVR32UC
100
400
MPUAPRA
MPU Access Permission Register A
101
404
MPUAPRB
MPU Access Permission Register B
102
408
MPUCR
MPU Control Register
103-191
412-764
Reserved
Reserved for future use
192-255
768-1020
IMPL
IMPLEMENTATION DEFINED
Table 9-3.
System Registers (Continued)
Reg #
Address
Name
Function
32058K
AVR32-01/12
相關(guān)PDF資料
PDF描述
MR80C52TXXX-16/883:RD 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
MJ80C32U-25:D MICROCONTROLLER
MQ80C32E-36:RD 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44
S80C32-40:R 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52EXXX-30:D 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44
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