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型號(hào)：	MR80C52CXXX-36SHXXX:R
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)：	111/849頁(yè)
文件大?。?/td>	12530K

32099I–01/2012

AT32UC3L016/32/64

120MHz RC Oscillator (RC120M)

Rev: 1.0.1.0

The 120MHz RC Oscillator can be used as source for the main clock in the device, as described

in the Power Manager chapter. The oscillator can also be used as source for the generic clocks,

as described in Generic Clock section. The RC120M must be enabled before it is used as a

source clock. To enable the clock, the user must write a one to the Enable bit in the 120MHz RC

Oscillator Control Register (RC120MCR.EN), and read back the RC120MCR register until the

EN bit reads one. The clock is disabled by writing a zero to RC120MCR.EN. The EN bit must be

read back as zero before the RC120M is re-enabled. If not, undefined behavior may occur.

The oscillator is automatically disabled in certain sleep modes to reduce power consumption, as

described in the Power Manager chapter.

Backup Registers (BR)

Rev: 1.0.0.1

Four 32-bit backup registers are available to store values when the device is in Shutdown

mode. These registers will keep their content even when the VDDCORE supply and the internal

regulator supply voltage supplies are removed. The backup registers can be accessed by read-

ing from and writing to the BR0, BR1, BR2, and BR3 registers.

After writing to one of the backup registers the user must wait until the Backup Register Interface

Ready bit in tne Power and Clocks Status Register (PCLKSR.BRIFARDY) is set before writing to

another backup register. Writes to the backup register while PCLKSR.BRIFARDY is zero will be

discarded. An interrupt can be generated on a zero-to-one transition on PCLKSR.BRIFARDY if

the BRIFARDY bit in the Interrupt Mask Register (IMR.BRIFARDY) is set. This bit is set by writ-

ing a one to the corresponding bit in the Interrupt Enable Register (IER.BRIFARDY).

After powering up the device the Backup Register Interface Valid bit in PCLKSR (PCLKSR.BRI-

FAVALID) is cleared, indicating that the content of the backup registers has not been written and

contains the reset value. After writing to one of the backup registers the PCLKSR.BRIFAVALID

bit is set. During writes to the backup registers (when BRIFARDY is zero) BRIFAVALID will be

zero. If a reset occurs when BRIFARDY is zero, BRIFAVALID will be cleared after the reset, indi-

cating that the content of the backup registers is not valid. If BRIFARDY is one when a reset

occurs, BRIFAVALID will be one and the content is the same as before the reset.

The user must ensure that BRIFAVALID and BRIFARDY are both set before reading the backup

32kHz RC Oscillator (RC32K)

Rev: 1.0.0.0

The RC32K can be used as source for the generic clocks, as described in The Generic Clocks

The 32 kHz RC oscillator (RC32K) is forced on after reset, and output on PA20. The clock is

available on the pad until the PPCR.FRC32 bit in the Power Manager has been cleared or a dif-

ferent peripheral function has been chosen on PA20 (PA20 will start with peripheral function F

by default). Note that the forcing will only enable the clock output. To be able to use the RC32K

normally the oscillator must be enabled as described below.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
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