32
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure
stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock
frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
8.9
Clock output buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when chip
clock is used to drive other circuits on the system. The clock will be output also during reset and the normal opera-
tion of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscillator,
can be selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is the divided system
clock that is output (CKOUT Fuse programmed).
8.10
System clock prescaler
The Atmel ATmega16M1/32M1/64M1 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is
low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all syn-
chronous peripherals. clk
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the
clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency correspond-
ing to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that
implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock
frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS
values are written, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this inter-
val, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding
to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the
CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.