參數(shù)資料
型號(hào)： MR80C52CXXX-16P883R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁(yè)數(shù)： 12/46頁(yè)
文件大小： 7004K
代理商： MR80C52CXXX-16P883R
144
7593L–AVR–09/12
AT90USB64/128
Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the coun-
ter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-
cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register B (OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Com-
pare Register A (OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.
OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.
Bit 0 – TOVn: Timer/Countern, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOVn Flag is set when the timer overflows. Refer to Table 15-4 on page 138 for the TOVn
Flag behavior when using another WGMn3:0 bit setting.
TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.
Alternatively, TOVn can be cleared by writing a logic one to its bit location.
相關(guān)PDF資料
PDF描述
MC80C52XXX-25/883:D 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40
MD80C52XXX-12SHXXX:D 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-20/883:RD 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44
MR80C52EXXX-12:RD 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
MQ80C52CXXX-30/883:R 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
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