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參數(shù)資料
| 型號： | MR80C52CXXX-12SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 9/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MR80C52CXXX-12SHXXX |
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200
2466T–AVR–07/10
ATmega16(L)
Several different scenarios may arise during arbitration, as described below:
Two or more Masters are performing identical communication with the same Slave. In this
case, neither the Slave nor any of the Masters will know about the bus contention.
Two or more Masters are accessing the same Slave with different data or direction bit. In this
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The Masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing Masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
Two or more Masters are accessing different Slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will
lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if
they are being addressed by the winning Master. If addressed, they will switch to SR or ST
mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they
will switch to not addressed Slave mode or wait until the bus is free and transmit a new
START condition, depending on application software action.
This is summarized in Figure 96. Possible status values are given in circles.
Figure 96. Possible Status Codes Caused by Arbitration
Own
Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Yes
Write
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Read
B0
68/78
38
SLA
START
Data
STOP
相關(guān)PDF資料 |
PDF描述 |
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| MC80C52CXXX-12SB | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32-25SCD | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C32E-20SHXXX:D | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52CXXX-16SCD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MF180C51-16R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
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