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| 型號(hào)： | MR80C32E-36SCD |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 145/224頁(yè) |
| 文件大小： | 24907K |
| 代理商： | MR80C32E-36SCD |
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331
32145C–06/2013
AT32UC3L0128/256
Write a zero to the MODE.REFCEN to disable he clock, without changing the other bits/fields
in the Mode register.
Wait until the SR.RCLKBUSY bit reads as zero.
17.5.1.1
Cautionary note
Note that if clock selected as source for CLK_REF is stopped during a measurement, this will
not be detected by the FREQM. The BUSY bit in the STATUS register will never be cleared, and
the DONE interrupt will never be triggered. If the clock selected as soruce for CLK_REF is
stopped, it will not be possible to change the source for the reference clock as long as the
selected source is not running.
17.5.2
Measurement
In the Mode Register the Clock Source Selection (CLKSEL) field selects CLK_MSR and the
Number of Reference Clock Cycles (REFNUM) field selects the duration of the measurement.
The duration is given in number of CLK_REF periodes.
Writing a one to the START bit in the Control Register (CTRL) starts the measurement. The
BUSY bit in SR is cleared when the measurement is done.
The result of the measurement can be read from the Value Register (VALUE). The frequency of
the measured clock CLK_MSR is then:
f
CLK_MSR = (VALUE/REFNUM)*fCLK_REF
17.5.3
Interrupts
The FREQM has two interrupt sources:
DONE: A frequency measurement is done
RCLKRDY: The reference clock is ready
These will generate an interrupt request if the corresponding bit in the Interrupt Mask Register
(IMR) is set. The interrupt sources are ORed together to form one interrupt request. The FREQM
will generate an interrupt request if at least one of the bits in the Interrupt Mask Register (IMR) is
set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register
(IER) and cleared by writing a one to this bit in the Interrupt Disable Register (IDR). The interrupt
request remains active until the corresponding bit in the Interrupt Status Register (ISR) is
cleared by writing a one to this bit in the Interrupt Clear Register (ICR). Because all the interrupt
sources are ORed together, the interrupt request from the FREQM will remain active until all the
bits in ISR are cleared.
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