
106
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
Figure 15-8. Analog Input Circuitry
Note:
The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic
capacitance inside the device. The value given is worst case.
15.9
Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measure-
ments. When conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
Keep analog signal paths as short as possible.
Make sure analog tracks run over the analog ground plane.
Keep analog tracks well away from high-speed switching digital tracks.
If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
Place bypass capacitors as close to V
CC and GND pins as possible.
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in
Sec-tion 15.7 on page 105. This is especially the case when system clock frequency is above 1 MHz, or when the ADC
design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction
Mode
15.10 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF in 2
n steps (LSBs). The lowest code
is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior, as follows:
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal
value: 0 LSB.
ADCn
IIH
1..100 k
ohm
CS/H= 14 pF
VCC/2
IIL