參數(shù)資料
型號: MQ80C52XXX-36SHXXX
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
封裝: CERAMIC, QFP-44
文件頁數(shù): 64/132頁
文件大小: 10886K
代理商: MQ80C52XXX-36SHXXX
269
8151H–AVR–02/11
ATmega128A
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
hold,max
24.14 ATmega128A Boundary-scan Order
Table 24-7 shows the Scan order between TDI and TDO when the Boundary-scan Chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In Figure 24-5, PXn. Data corresponds to FF0, PXn. Control
corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is
not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
6
Verify the
COMP bit
scanned out
to be 0
1
0x200
0x08
1
0
7
1
0x200
0x08
0
1
0
8
1
0x200
0x08
1
0
9
1
0x143
0x08
1
0
10
1
0x143
0x08
1
0
11
Verify the
COMP bit
scanned out
to be 1
1
0x200
0x08
1
0
Table 24-6.
Algorithm for Using the ADC
Step
Actions
ADCEN
DAC
MUXEN
HOLD
PRECH
PA3.
Data
PA3.
Control
PA3.
Pullup_
Enable
Table 24-7.
ATmega128A Boundary-scan Order
Bit Number
Signal Name
Module
204
AC_IDLE
Comparator
203
ACO
202
ACME
201
AINBG
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