245
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Figure 23-1. Analog-to-digital Converter block schematic.
23.3
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
the AREF pin minus 1LSB. Optionally, AV
CC or an internal 2.56V reference voltage may be con-
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve
noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can
be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as
positive and negative inputs to the differential gain amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage difference
between the selected input channel pair by the selected gain factor. This amplified value then
ADC CONVERSION
COMPLETE IRQ
8-BIT DATABUS
15
0
ADIE
AD
A
T
E
ADSC
ADE
N
ADIF
MUX[4:0]
ADPS[2:0]
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
(1.1V/2.56V)
AVCC
REFS[1:0]
ADLAR
CHA
NN
EL
SELECTIO
N
ADC[9:0]
ADC
MULTIPLEXER
OUTPUT
GAIN
AMPLIFIER
AREF
BANDGAP (1.1V)
REFERENCE
GND
CONVERSION LOGIC
ADC CTRL & STATUS
REGISTER B (ADCSRB)
ADC CTRL & STATUS
REGISTER A (ADCSRA)
PRESCALER
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
DIFF
/
GAI
N
SELECT
ADC DATA REGISTER
(ADCH/ADCL)
ADC[2:0]
TRIGGER
SELECT
START
INTERRUPT
FLAGS
ADTS[2:0]
+
-
NEG
INPUT
MUX
POS
INPUT
MUX
ADC[7:0]
+
-
10-bit DAC