94
32000D–04/2011
AVR32
[i:j]
Denotes bit i to j in an immediate value.
Some instructions access or use doubleword operands. These operands must be
placed in two consecutive register addresses where the first register must be an even
register. The even register contains the least significant part and the odd register con-
tains the most significant part. This ordering is reversed in comparison with how data is
organized in memory (where the most significant part would receive the lowest address)
and is intentional.
The programmer is responsible for placing these operands in properly aligned register
pairs. This is also
specified in the "Operands" section in the detailed description of each instruction. Fail-
ure to do so will
result in an undefined behaviour.
9.1.2
Operator Symbols
∧
Bitwise logical AND operation.
∨
Bitwise logical OR operation.
Bitwise logical EOR operation.
Bitwise logical NOT operation.
Sat
Saturate operand
9.1.3
Operations
ASR(x, n)
SE(x, Bits(x) + n) >> n
Bits(x)
Number of bits in operand x
LSR(x, n)
x >> n
LSL(x, n)
x << n
SATS(x, n)
Signed Saturation ( x is treated as a signed value ):
If (x > (2n-1-1)) then (2n-1-1); elseif (x < -2n-1) then -2n-1; else x;
SATSU(x, n)
Signed to Unsigned Saturation ( x is treated as a signed value ):
If (x > (2n-1)) then (2n-1-1); elseif ( x < 0 ) then 0; else x;
SATU(x, n)
Unsigned Saturation ( x is treated as an unsigned value ):
If (x > (2n-1)) then (2n-1-1); else x;
SE(x, n)
Sign Extend x to an n-bit value
SE(x)
Identical to SE(x, 32)
ZE(x, n)
Zero Extend x to an n-bit value
ZE(x)
Identical to ZE(x, 32)
9.1.4
Status Register Flags
C:
Carry / Borrow flag.
Z:
Zero flag, set if the result of the operation is zero.
N:
Bit 31 of the result.
V:
Set if 2’s complement overflow occurred.
Q:
Saturated flag, set if saturation and/or overflow has occurred after some
instructions.
M0:
Mode bit 0