
14
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
7.7
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) gives the page number and the least significant address bits (FWORD)
gives the word in the page.
Table 7-2.
Number of words and Pages in the Flash.
PROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives
the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3.
Number of bytes and Pages in the EEPROM.
Devices
Flash
Page Size
FWORD
FPAGE
Application
Boot
Size
(words)
Size
No of Pages
Size
No of Pages
ATxmega64A3
64 KB + 4 KB
128
Z[7:1]
Z[16:8]
64K
256
4 KB
16
ATxmega128A3
128 KB + 8 KB
256
Z[8:1]
Z[17:9]
128K
256
8 KB
16
ATxmega192A3
192 KB + 8 KB
256
Z[8:1]
Z[18:9]
192K
384
8 KB
16
ATxmega256A3
256 KB + 8 KB
256
Z[8:1]
Z[18:9]
256K
512
8 KB
16
Devices
EEPROM
Page Size
E2BYTE
E2PAGE
No of Pages
Size
(Bytes)
ATxmega64A3
2 KB
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega128A3
2 KB
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega192A3
2 KB
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega256A3
4 KB
32
ADDR[4:0]
ADDR[11:5]
128