18
ATmega8A [DATASHEET]
8159E–AVR–02/2013
be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to
these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will
operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI
and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
8.6
Register Description
8.6.1
EEARH and EEARL – The EEPROM Address Register
Bits 15:9 – Res: Reserved Bits
These bits are reserved bits in the ATmega8A and will always read as zero.
Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512 bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is
undefined. A proper value must be written before the EEPROM may be accessed.
8.6.2
EEDR – The EEPROM Data Register
Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the
address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from
the EEPROM at the address given by EEAR.
8.6.3
EECR – The EEPROM Control Register
Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8A and will always read as zero.
Bit
15
141312
1110
9
8
––––
–––
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7654
3210
Read/Write
RRR
RRRR
R/W
Initial Value
0000
000
X
XX
XXXX
XX
Bit
7654
3210
MSB
LSB
EEDR
Read/Write
R/W
Initial Value
0000
Bit
7654
3210
–
EERIE
EEMWE
EEWE
EERE
EECR
Read/Write
R
R/W
Initial Value
0000
00
X
0