29
7707F–AVR–11/10
AT90USB82/162
6.2.5
Clock Status Register – CLKSTA
Bit 7-2 - Reserved bits
These bits are reserved and will always read as zero.
Bit 1 – RCON: RC Oscillator On
This bit is set by hardware to one if the RC Oscillator is running.
This bit is set by hardware to zero if the RC Oscillator is stoped.
Bit 0 – EXTON: External Oscillator / Low Power Oscillator On
This bit is set by hardware to one if the External Oscillator / Low Power Oscillator is running.
This bit is set by hardware to zero if the External Oscillator / Low Power Oscillator is stoped.
6.3
Clock Sources
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
6.3.1
Default Clock Source
The device is shipped with low power crystal oscillator and with the fuse CKDIV8 programmed.
The startup time is set to maximum and time-out period enabled. (CKSEL = "1110", SUT = "01",
CKDIV8 = "0").
6.3.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
describes the start conditions for the internal reset. The delay (t
TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in
Table 6-2. The frequency of the Watchdog Oscillator is voltage
Bit
7
6
543
2
1
0
-
RCON
EXTON
CLKSTA
Read/Write
R
Initial Value
0
See Bit Description
Table 6-1.
Device Clocking Options Select
Device Clocking Option
CKSEL3..0
Low Power Crystal Oscillator
1111 - 1000
Reserved
0111 - 0110
Reserved
0101 - 0100
Reserved
0011
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0001