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參數(shù)資料
| 型號： | MQ80C52CXXX-30/883D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 43/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MQ80C52CXXX-30/883D |
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243
XMEGA A [MANUAL]
8077I–AVR–11/2012
21.10 USART in Master SPI Mode
Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled to
serve as the serial input. The XCK pin will be used as the transfer clock.
As for the USART, a data transfer is initiated by writing to the DATA register. This is the case for both sending and
receiving data, since the transmitter controls the transfer clock. The data written to DATA are moved from the transmit
buffer to the shift register when the shift register is ready to send a new frame.
The transmitter and receiver interrupt flags and corresponding USART interrupts used in master SPI mode are identical
in function to their use in normal USART operation. The receiver error status flags are not in use and are always read as
zero.
Disabling of the USART transmitter or receiver in master SPI mode is identical to their disabling in normal USART
operation.
21.11 USART SPI vs. SPI
The USART in master SPI mode is fully compatible with the standalone SPI module in that:
Timing diagrams are the same
UCPHA bit functionality is identical to that of the SPI CPHA bit
UDORD bit functionality is identical to that of the SPI DORD bit
When the USART is set in master SPI mode, configuration and use are in some cases different from those of the
standalone SPI module. In addition, the following differences exist:
The USART transmitter in master SPI mode includes buffering, but the SPI module has no transmit buffer
The USART receiver in master SPI mode includes an additional buffer level
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Max
2.0Mbps
4.0Mbps
Baud
fOSC = 32.0000MHz
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