16
XMEGA C4 [DATASHEET]
8493G–AVR–01/2014
7.10
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.11
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 16 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
Table 7-2.
Number of words and pages in the flash.
Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or
one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address
register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number
and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
Number of bytes and pages in the EEPROM.
Devices
PC size
Flash size
Page size
FWORD
FPAGE
Application
Boot
bits
bytes
words
Size
No of pages
Size
No of pages
ATxmega16C4
17
16K + 4K
128
Z[6:0]
Z[13:7]
16K
64
4K
16
ATxmega32C4
18
32K + 4K
128
Z[6:0]
Z[14:7]
32K
128
4K
16
Devices
EEPROM
Page size
E2BYTE
E2PAGE
No of pages
Size
bytes
ATxmega16C4
1K
32
ADDR[4:0]
ADDR[10:5]
32
ATxmega32C4
1K
32
ADDR[4:0]
ADDR[10:5]
32