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32000D–04/2011
AVR32
6.2.1.3
MPU Cacheable Register A / B- MPUCRA / MPUCRB
The MPUCR registers have one bit per region, indicating if the region is cacheable. If the corre-
sponding bit is set, the region is cacheable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUCR registers.
6.2.1.4
MPU Bufferable Register A / B- MPUBRA / MPUBRB
The MPUBR registers have one bit per region, indicating if the region is bufferable. If the corre-
sponding bit is set, the region is bufferable. The register is written to 0 upon reset.
AVR32UC implementations may optionally choose not to implement the MPUBR registers.
6.2.1.5
MPU Access Permission Register A / B - MPUAPRA / MPUAPRB
The MPUAPR registers indicate the access permissions for each region. The MPUAPR is writ-
6.2.1.6
MPU Control Register - MPUCR
The MPUCR controls the operation of the MPU. The MPUCR has only one field:
E - Enable. If set, the MPU address checking is enabled. If cleared, the MPU address
checking is disabled and no exceptions will be generated by the MPU.
6.2.2
MPU exception handling
This chapter describes the exceptions that can be signalled by the MPU.
6.2.2.1
ITLB Protection Violation
An ITLB protection violation is issued if an instruction fetch violates access permissions. The vio-
lating instruction is not executed. The address of the failing instruction is placed on the system
stack.
Table 6-3.
Access permissions implied by the APn bits
AP
Privileged mode
Unprivileged mode
B’0000
Read
None
B’0001
Read / Execute
None
B’0010
Read / Write
None
B’0011
Read / Write / Execute
None
B’0100
Read
B’0101
Read / Execute
B’0110
Read / Write
B’0111
Read / Write / Execute
B’1000
Read / Write
Read
B’1001
Read / Write
Read / Execute
B’1010
None
Other
UNDEFINED