參數(shù)資料
型號： MQ80C32-25/883:D
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù)： 108/109頁
文件大?。?/td> 10824K
810
32117D–AVR-01/12
AT32UC3C
set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit
channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is trans-
mitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current
transmit channel number is transmitted.
Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left
sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data
word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses
bits 15 through 8 of the same data word.
30.6.9
DMA Operation
The Receiver and the Transmitter can each be connected either to one single Peripheral DMA
channel or to one Peripheral DMA channel per data channel. This is selected by writing to the
MR.RXDMA and MR.TXDMA bits. If a single Peripheral DMA channel is selected, all data sam-
ples use IISC Receiver or Transmitter DMA channel 0.
The Peripheral DMA reads from the RHR register and writes to the RHR register for all audio
channels, successively.
The Peripheral DMA transfers may use 32-bit word, 16-bit halfword, or 8-bit byte according to
the value of the MR.DATALENGTH field.
30.6.10
Loop-back Mode
For debugging purposes, the IISC can be configured to loop back the Transmitter to the
Receiver. Writing a one to the MR.LOOP bit will internally connect ISDO to ISDI, so that the
transmitted data is also received. Writing a zero to MR.LOOP will restore the normal behavior
with independent Receiver and Transmitter. As for other changes to the Receiver or Transmitter
configuration, the IISC Receiver and Transmitter must be disabled before writing to the MR reg-
ister to update MR.LOOP.
30.6.11
Interrupts
An IISC interrupt request can be triggered whenever one or several of the following bits are set
in the Status Register (SR): Receive Ready (RXRDY), Receive Overrun (RXOR), Transmit
Ready (TXRDY), or Transmit Underrun (TXOR).
The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one the corresponding bit in the Status Clear Register (SCR).
For debugging purposes, interrupt requests can be simulated by writing a one to the correspond-
ing bit in the Status Set Register (SSR).
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