341
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Notes:
1. In Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, this parameter is characterized and not 100% tested.
2. Required only for f
SCL > 100kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency.
5. This requirement applies to all Atmel ATmega32 two-wire Serial Interface operation. Other devices connected to the two-
wire Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega32 two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than
6MHz for the low time requirement to be strictly met at f
SCL = 100kHz.
7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement
will not be strictly met for f
SCL > 308kHz when fCK = 8MHz. Still, ATmega32 devices connected to the bus may communicate
at full speed (400kHz) with other ATmega32 devices, as well as any other device with a proper t
LOW acceptance margin.
Figure 28-5. Two-wire serial bus timing.
tHIGH
High period of the SCL clock
f
SCL 100kHz
4.0
–
s
f
SCL > 100kHz
0.6
–
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz
4.7
–
f
SCL > 100kHz
0.6
–
t
HD;DAT
Data hold time
fSCL 100kHz
0
3.45
fSCL > 100kHz
0
0.9
tSU;DAT
Data setup time
f
SCL 100kHz
250
–
ns
fSCL > 100kHz
100
–
tSU;STO
Setup time for STOP condition
fSCL 100kHz
4.0
–
s
f
SCL > 100kHz
0.6
–
t
BUF
Bus free time between a STOP and
START condition
fSCL 100kHz
4.7
–
fSCL > 100kHz
1.3
–
Table 28-16. two-wire serial bus requirements. (Continued)
Symbol
Parameter
Condition
Min.
Max.
Units
tSU;STA
tLOW
tHIGH
tLOW
tof
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
SCL
SDA
tr