參數(shù)資料
型號(hào)： MPD800261F1-523-HN2
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA304
封裝： 19 X 19 MM, LEAD FREE, PLASTIC, FBGA-304
文件頁數(shù)： 17/45頁
文件大?。?/td> 369K
代理商： MPD800261F1-523-HN2
24
Preliminary Data Sheet A17989EE1V0DS00
PD800261
F_CLK
I
3.3 V CMOS
-
REF_CLK
O
-
3.3 V CMOS
-
6 mA
RESET_N
I
Schmitt
-
50 k
Ω pull up
-
P(2:1)TxN
I/O
Analog
-
P(2:1)TxP
I/O
Analog
-
P(2:1)TDxN Note 3
O
-
3.3 V CMOS
-
12 mA
P(2:1)TDxP Note 3
O
-
3.3 V CMOS
-
12 mA
P(2:1)RxN
I/O
Analog
-
P(2:1)RxP
I/O
Analog
-
P(2:1)RDxN
I
PECL
-
P(2:1)RDxP
I
PECL
-
P(2:1)SDxN
I
PECL
-
P(2:1)SDxP
I
PECL
-
EXTRES
I/O
Analog
-
TRST_N
I
Schmitt
-
TCK
I
Schmitt
-
50 k
Ω pull up
-
TDI
I
Schmitt
-
50 k
Ω pull up
-
TMS
I
Schmitt
-
50 k
Ω pull up
-
TDO
O
-
3.3 V CMOS
-
6 mA
SRST_N
I/O
Schmitt
3.3 V CMOS
50 k
Ω pull up
6 mA
TAP_SEL
I
Schmitt
-
50 k
Ω pull up
-
Notes: 1. The address pins A(23:15) and the DTR_N pin are used as inputs only during the active reset phase.
2. These pins have alternative functions, to which the pin characteristics apply as well. Note that the I/O
type given in Table 1-13 applies to the pin. I/O types that apply to one of the shared functions of a
specific pin are found in Tables 1-1 to 1-11.
3. These pins require external circuitry in order to provide PECL compliant output levels.
Remark:
Shared pins are not listed with all possible pin names. Please check Tables 1-1 to 1-10 for possible
pin names first, before looking up pin characteristics in Table 1-13.
Table 1-13:
Pin Characteristics (2/2)
Pin Name
I/O
Input type
Output type
Internal pull
up/down
Drive capability
IOH
IOL
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