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參數(shù)資料
| 型號： | MPC998FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 998 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 286K |
| 代理商： | MPC998FA |
4
MPC998
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
442
AC CHARACTERISTICS (VCCA = VCCI = 3.3V ± 5%, VCCO = 1.7V to 2.1V, TA = 0 to 70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
100 - 125
MHz
fMAX
Maximum Output Frequency
520
840
MHz
Note b
tsk(o)
Skew Error (PCLK)
35
ps
Note c
tjit(0)
Phase jitter (IO jitter)
output period / 2
Note c
tjit(cc)
Cycle–to–cycle jitter
(full period)
5%
Note c, e
tjit(1/2per)
Cycle–to–cycle jitter
(half period)
6%
Note c, d
VDIFout
Differential Output pk–pk swing
0.6
V
For all HSTL
output pairs
Vx
Differential output crosspoint
voltage
0.68
0.9
V
For all HSTL
output pairs
tlock
Maximum PLL lock time
10
ms
a) All PCLK outputs are terminated in 25
W to ground, EXTFB_OUT is terminated in 50W to ground (applies to all measurements).
b) With PLL active but in bypass mode, fref Max is limited by input buffer; best performance is expected with PECL input.
c) Measured at differential pair crossover.
d) Reference to half PCLK period.
e) Reference to full PCLK period.
Figure 3. HSTL Differential Input Levels
VCCO
VCMR
VDIF
VTR
VX
VCP
VEE
Figure 4. Output Termination and AC Test Reference
MPC998 Output
Z = 50
RT = 25
VTT = GND
For external feedback output
RT = 50W
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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