參數(shù)資料
型號(hào)： MPC9893AE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： 7 X 7 MM, LEAD FREE, LQFP-48
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 353K
代理商： MPC9893AE
Advanced Clock Drivers Device Data
6
Freescale Semiconductor
MPC9893
Table 8. AC Characteristics (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
FSEL=000x
FSEL=001x
FSEL=010x
FSEL=011x
FSEL=100x
FSEL=101x
FSEL=110x
FSEL=111x
15.0
30.0
40.0
30.0
60.0
15.0
30.0
60.0
25.0
50.0
66.6
50.0
100.0
12.5
50.0
100.0
MHz
PLL locked
fMAX
Maximum Output Frequency
FSEL=000x
FSEL=001x
FSEL=010x
FSEL=011x
FSEL=100x
FSEL=101x
FSEL=110x
FSEL=111x
60.0
30.0
60.0
7.5
15.0
30.0
200.0
100.0
200.0
25.0
50.0
100.0
MHz
PLL locked
frefDC
Reference Input Duty Cycle
40
60
%
tr, tf
CLK0, 1 Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay (static phase offset, CLKx to FB)
VCC=3.3 V±5% and FSEL[0:2]=111
VCC=3.3 V±5%
VCC=2.5 V±5% and FSEL[0:2]=111
VCC=2.5 V±5%
–60
–200
–125
–400
+50
+100
+25
+100
ps
PLL locked
t
Rate of Period Change (phase slew rate)
QAx outputs
QBx outputs (FSEL=xxx0)
QBx outputs (FSEL=xxx1)
150
300
ps/cycle
Failover switch
tsk(O)
Output-to-Output Skew(2)
(within bank)
(bank-to-bank)
(any output to QFB)
2. See application section for part-to-part skew calculation.
150
100
125
ps
DCO
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-Cycle Jitter(3)
FSEL3=0
FSEL3=1
3. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section.
225
425
ps
See applications
section
tJIT(PER)
Period Jitter(3)
FSEL3=0
FSEL3=1
150
250
ps
See applications
section
tJIT()
I/O Phase Jitter(4)
FB=4: FSEL[0:2]=100 or 111
RMS (1
σ)
FB=6: FSEL[0:2]=010
RMS (1
σ)
FB=8: FSEL[0:2]=001, 011, or 110
RMS (1
σ)
FB=16: FSEL[0:2]=000 or 101
RMS (1
σ)
4. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See APPLICATIONS INFORMATION for more information
and for the calculation for other confidence factors than 1
σ.
40
50
55
70
ps
See applications
section
BW
PLL Closed Loop Bandwidth(5)
FSEL=111x
5. –3dB point of PLL transfer characteristics.
0.8-4.0
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9893AER2 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9893FA 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9893FAR2 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 48-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9893FAR2 - Tape and Reel
MPC9894 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Input Redundant IDCS Clock Generator
MPC9894VM 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL
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