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參數(shù)資料
| 型號： | MPC9773AE |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| 標準包裝： | 160 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:12 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 242.5MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-TQFP（10x10） |
| 包裝： | 托盤 |
MPC9773 REVISION 6 JANUARY 31, 2013
14
2013 Integrated Device Technology, Inc.
MPC9773 Data Sheet
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9773 clock driver. For the series terminated
case, however, there is no DC current draw; thus the outputs
can drive multiple series terminated lines. Figure 12
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC9773 clock driver is
effectively doubled due to its capability to drive multiple lines.
Figure 12. Single versus Dual Transmission Lines
The waveform plots in Figure 13 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9773 output buffer
is more than sufficient to drive 50-
transmission lines on the
incident edge. Note from the delay measurements in the
simulations that a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9773. The output waveform
in Figure 13 shows a step in the waveform. This step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the
36-
series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL =VS (Z0 (RS + R0 + Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 (18+17+25)
=1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
1.
Final skew data pending specification.
Figure 13. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 14 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
Figure 14. Optimized Dual Line Termination
14
In
MPC9773
Output
Buffer
RS = 36
ZO = 50
OutA
14
In
MPC9773
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
Time (ns)
Volt
age
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC9773
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 22 = 50 || 50
25
= 25
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9773AER2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773FA | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9773FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 52-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9773FAR2 - Tape and Reel |
| MPC9774 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC9774AE | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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