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參數(shù)資料
| 型號： | MPC9772FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 240 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 238K |
| 代理商： | MPC9772FAR2 |
MPC9772
TIMING SOLUTIONS
13
MOTOROLA
The waveform plots in Figure 13. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9772 output buffer is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9772. The output waveform in Figure 13. “Single versus
Dual Line Termination Waveforms” shows a step in the
waveform, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36
series resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS (Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 14. “Optimized Dual Line Termination” should be
used. In this case the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
Figure 12. Single versus Dual Transmission Lines
14
IN
MPC9772
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC9772
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
Figure 13. Single versus Dual Waveforms
TIME (ns)
VO
LTAG
E
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Figure 14. Optimized Dual Line Termination
14
MPC9772
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
= 25
Figure 15. CCLK MPC9772 AC Test Reference
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9772 DUT
VTT
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