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參數(shù)資料
| 型號： | MPC96877VK |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DRIVER 1:10 SDRAM 52-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標準包裝： | 1 |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR2，SDRAM |
| 輸入： | 時鐘 |
| 輸出： | SSTL-18 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 340MHz |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-BGA |
| 包裝： | 托盤 |
MPC96877
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
553
NOTES:
1. There are two different terminations that are used with the following tests. The loadboard in Figure 2. IBIS Model Output Load is used to measure
the input and output differential-pair cross voltage only. The loadboard in Figure 3. Output Load Test Circuit 1 is used to measure all other tests.
For consistency, equal length cables must be used.
2. Static Phase offset does not include Jitter.
3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
4. The Output Slew Rate is determined form the IBIS model into the load shown in Figure 4. Output Load Test Circuit 2. It is measured single ended.
5. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with these
Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2
DIMM application.
Table 7. Switching Characteristics over Recommended Free-Air Operating Temperature Range Unless Otherwise Noted
(see Notes)
Description
Parameter
Diagram
AVDD, VDDQ = 1.8 V ± 0.1 V
Unit
Min
Nom
Max
OE to any Y/Y
ten
see Figure 11
8
ns
OE to any Y/Y
tdis
see Figure 11
8
ns
Cycle-to-Cycle period jitter
tjit(cc+)
see Figure 4
0
40
ps
tjit(cc–)
0
–40
ps
Static phase offset
t(
)
see Figure 5
–50
50
ps
Dynamic phase offset
t(
)dyn
see Figure 10
–50
50
ps
Output clock skew
tsk(o)
see Figure 6
40
ps
Period Jitter
tjit(per)
see Figure 7
–40
40
ps
Half -period jitter
tjit(hper)
see Figure 8
–75
75
ps
Output Enable
slr(i)
see Figure 3
and Figure 9
0.5
V/ns
Input clock slew rate, measured single ended
1
2.5
4
Output clock slew rate, measured single ended
slr(o)
see Figure 3
and Figure 9
1.5
2.5
3
V/ns
Output differential-pair cross voltage
VOX
see Figure 2
(VDDQ/2) – 0.1
(VDDQ/2) + 0.1
V
SSC modulation frequency
30
33
kHz
SSC clock input frequency deviation
0.0
–0.5
PLL Loop bandwidth (–3dB from unity gain)
2.0
MHz
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
NETCOM
IDT 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
7
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