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參數(shù)資料
| 型號： | MPC962309EJ-1HR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER ZD 1:5 3.3V 16-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 扇出緩沖器（分配），零延遲緩沖 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133.33MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
DATASHEET
Low-Cost, 3.3V Zero Delay Buffer
MPC962305
NRND
MPC962305 REVISION 8 JANUARY 8, 2013
1
2013 Integrated Device Technology, Inc.
The MPC962309 is a zero delay buffer designed to distribute high-speed
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin
version of the MPC962309 which drives five outputs with one reference input.
The -1H versions of these devices have higher drive than the -1 devices and can
operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which
lock to an input clock presented on the REF pin. The PLL feedback is on-chip and
is obtained from the CLOCKOUT pad.
Features
1:5 LVCMOS zero-delay buffer (MPC962305)
1:9 LVCMOS zero-delay buffer (MPC962309)
Zero input-output propagation delay
Multiple low-skew outputs
250 ps max output-output skew
700 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium based
systems
Test Mode to bypass PLL (MPC962309 only. See Table 3)
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin
TSSOP package (MPC962309), all Pb-free
Single 3.3 V supply
Ambient temperature range: –40
C to +85C
Compatible with the CY2305, CY23S05, CY2309, CY23S09
Spread spectrum compatible
Not Recommend for New Designs
Use replacement part IDT2305
The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank
B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs
for chip and system testing purposes.
The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During
this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0
A of current draw for the device. The
PLL shuts down in one additional case as shown in Table 3.
Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this
situation, the difference between the output skews of two devices will be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to
be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information
page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and
MPC962309-1H, are available to provide faster rise and fall times of the base device.
Pentium II is a trademark of Intel Corporation.
MPC962305
MPC962309
EF SUFFIX
8-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751-06
EJ SUFFIX
8-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948J-01
EF SUFFIX
16-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751B-05
EJ SUFFIX
16-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948F-01
NRND – Not Recommend for New Designs
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