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參數(shù)資料
| 型號(hào)： | MPC962309DT-1H |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, TSSOP-16 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大小： | 110K |
| 代理商： | MPC962309DT-1H |
MPC962305
508
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Table 1. Pin Description for MPC962309
Pin
Signal
Description
1
REF1
Input reference frequency, 5 V-tolerant input
2
CLKA12
Buffered clock output, Bank A
3
CLKA22
Buffered clock output, Bank A
4VDD
3.3 V supply
5
GND
Ground
6
CLKB12
Buffered clock output, Bank B
7
CLKB22
Buffered clock output, Bank B
8
S23
Select input, bit 2
9
S13
Select input, bit 1
10
CLKB32
Buffered clock output, Bank B
11
CLKB42
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3 V supply
14
CLKA32
Buffered clock output, Bank A
15
CLKA42
Buffered clock output, Bank A
16
CLKOUT2
Buffered output, internal feedback on this pin
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
SOIC/TSSOP
Top View
Pin Configuration
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
PLL
MUX
Select Input
Decoding
S2
S1
REF
Block Diagram
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
REF
CLK2
CLK1
GND
SOIC/TSSOP
Top View
Table 2. Pin Description for MPC962305
Pin
Signal
Description
1
REF1
Input reference frequency, 5 V-tolerant input
2
CLK22
Buffered clock output
3
CLK12
Buffered clock output
4
GND
Ground
5
CLK32
Buffered clock output
6
VDD
3.3 V supply
7
CLK42
Buffered clock output
8
CLKOUT2
Buffered clock output, internal feedback on this pin3
1.
Weak pull-down.
2.
Weak pull-down on all outputs.
3.
Weak pull-ups on these inputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC962309D-1R2 | 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962305EF-1HR2 | 962305 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MPC962309EF-1H | 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962305D-1R2 | 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MPC962309EF-1HR2 | 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC962309DT-1HR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962309EF-1 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Low-Cost, 3.3V Zero Delay Buffer |
| MPC962309EF-1H | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC962309EF-1HR2 | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC962309EF-1R2 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Low-Cost, 3.3V Zero Delay Buffer |
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