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參數(shù)資料
| 型號： | MPC962308D-2R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 96K |
| 代理商： | MPC962308D-2R2 |
MPC962308
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
517
Table 16. Switching Characteristics for MPC962308-X Industrial Temperature Devices1
1.
All parameters are specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load, All devices
10
100
MHz
t1
Output Frequency2
2.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
20-pF load, -1H, -5H devices
10
133.3
MHz
t1
Output Frequency2
15-pF load, -1, -2, -3, -4 devices
10
133.3
MHz
Duty Cycle2 = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT =66.66 MHz
30-pF load
40.0
60.0
%
Duty Cycle2 = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT <50.0 MHz
15-pF load
45.0
55.0
%
t3
Rise Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
30-pF load
2.50
ns
Rise Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
15-pF load
1.50
ns
Rise Time2
(-1H, -5H)
Measured between 0.8 V and 2.0 V,
30-pF load
1.50
ns
t4
Fall Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
30-pF load
2.50
ns
Fall Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
15-pF load
1.50
ns
Fall Time2
(-1H, -5H)
Measured between 0.8 V and 2.0 V,
30-pF load
1.25
ns
Output-to-Output Skew on
same Bank (-1, -2, -3, -4)2
All outputs equally loaded
200
ps
t5
Output-to-Output Skew
(-1H, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output
Bank B Skew (-1, -4, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output
Bank B Skew (-2, -3)
All outputs equally loaded
400
ps
t6
Delay, REF Rising Edge to
FBK Rising Edge2
Measured at VDD/2
0
±250
ps
t7
Device-to-Device Skew2
Measured at VDD/2 on the FBK pins of devices
0
700
ps
t8
Output Slew Rate2
Measured between 0.8 V and 2.0 V on -1H,
-5H device using Test Circuit # 2
1
V/ns
tJ
Cycle-to-Cycle Jitter
(-1, -1H, -4, -5H)2
Measured at 66.67 MHz, loaded outputs,
15-pF load
200
ps
Measured at 66.67 MHz, loaded outputs,
30-pF load
200
ps
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
ps
tJ
Cycle-to-Cycle Jitter
(-2, -3)2
Measured at 66.67 MHz, loaded outputs
30-pF load
400
ps
Measured at 66.67 MHz, loaded outputs
15-pF load
400
ps
tLOCK
PLL Lock Time2
Stable power supply, valid clocks presented
on REF and FBK pins
1.0
ms
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