參數(shù)資料
型號： MPC962305EJ-1HR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 時鐘及定時
英文描述： 962305 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝： 0.150 INCH, TSSOP-8
文件頁數(shù)： 4/6頁
文件大?。?/td> 110K
代理商： MPC962305EJ-1HR2
MPC962305
510
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices1
1.
All parameters are specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load
10-pF load
10
100
133.33
MHz
Duty Cycle2 = t2 ÷ t1
2.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
Measured at 1.4 V, FOUT = 66.67 MHz
40.0
50.0
60.0
%
t3
Rise Time2
Measured between 0.8 V and 2.0 V
2.50
ns
t4
Fall Time2
Measured between 0.8 V and 2.0 V
2.50
ns
t5
Output to Output Skew2
All outputs equally loaded
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge2
Measured at VDD/2
0
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge2
Measured at VDD/2. Measured in PLL Bypass Mode,
MPC962309 device only
15
8.7
ns
t7
Device to Device Skew2
Measured at VDD/2 on the CLKOUT pins of devices
0700
ps
tJ
Cycle to Cycle Jitter2
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time2
Stable power supply, valid clock presented on REF pin
1.0
ms
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices1
1.
All parameters are specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load
10-pF load
10
100
133.33
MHz
Duty Cycle2 = t2
÷ t1
2.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
Measured at 1.4 V, FOUT = 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle2 = t2
÷ t1
Measured at 1.4 V, FOUT < 50 MHz
45.0
55.0
%
t3
Rise Time2
Measured between 0.8 V and 2.0 V
1.50
ns
t4
Fall Time2
Measured between 0.8 V and 2.0 V
1.50
ns
t5
Output to Output Skew2
All outputs equally loaded
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge2
Measured at VDD/2
0
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge2
Measured at VDD/2. Measured in PLL Bypass Mode,
MPC962309 device only
15
8.7
ns
t7
Device to Device Skew2
Measured at VDD/2 on the CLKOUT pins of devices
0700
ps
t8
Output Slew Rate2
Measured between 0.8 V and 2.0 V using Test Circuit #2
1V/ns
tJ
Cycle to Cycle Jitter2
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time2
Stable power supply, valid clock presented on REF pin
1.0
ms
相關(guān)PDF資料
PDF描述
MPC962305D-1 962305 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
MPC962309DT-1H 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MPC962309D-1R2 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MPC962305EF-1HR2 962305 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
MPC962309EF-1H 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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參數(shù)描述
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