- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26839 > MPC962305D-1R2 (INTEGRATED DEVICE TECHNOLOGY INC) 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 PDF資料下載
參數(shù)資料
| 型號： | MPC962305D-1R2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 525K |
| 代理商： | MPC962305D-1R2 |
MPC962305
LOW-COST, 3.3V ZERO DELAY BUFFER
IDT / ICS 3.3V ZERO DELAY BUFFER
2
MPC962305 REV 7 JULY 16, 2007
Table 1. Pin Description for MPC962309
Pin
Signal
Description
1REF(1)
1. Weak pull-down.
Input reference frequency, 5 V-tolerant input
2
CLKA1(2)
2. Weak pull-down on all outputs.
Buffered clock output, Bank A
3
CLKA2(2)
Buffered clock output, Bank A
4VDD
3.3 V supply
5
GND
Ground
6
CLKB1(2)
Buffered clock output, Bank B
7
CLKB2(2)
Buffered clock output, Bank B
8S2(3)
3. Weak pull-ups on these inputs.
Select input, bit 2
9S1(3)
Select input, bit 1
10
CLKB3(2)
Buffered clock output, Bank B
11
CLKB4(2)
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3 V supply
14
CLKA3(2)
Buffered clock output, Bank A
15
CLKA4(2)
Buffered clock output, Bank A
16
CLKOUT(2)
Buffered output, internal feedback on this pin
Table 2. Pin Description for MPC962305
Pin
Signal
Description
1
REF(1)
1. Weak pull-down.
Input reference frequency, 5 V-tolerant input
2
CLK2(2)
2. Weak pull-down on all outputs.
Buffered clock output
3
CLK1(2)
Buffered clock output
4
GND
Ground
5
CLK3(2)
Buffered clock output
6
VDD
3.3 V supply
7
CLK4(2)
Buffered clock output
8
CLKOUT(2)
Buffered clock output, internal feedback on this pin
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
SOIC/TSSOP
Top View
Pin Configuration
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
PLL
MUX
Select Input
Decoding
S2
S1
REF
Block Diagram
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
REF
CLK2
CLK1
GND
SOIC/TSSOP
Top View
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC962309EF-1HR2 | 962309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962305EF-1H | 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MPC962305DT-1H | 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MPC9653AACR2 | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9653AFA | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC962305DT-1H | 功能描述:IC CLOCK BUFFER 1:5 8-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC962305DT-1HR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305EF-1 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Low-Cost, 3.3V Zero Delay Buffer |
| MPC962305EF-1H | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC962305EF-1HR2 | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。