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參數(shù)資料
| 型號： | MPC949 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE 1:15 PECL TO CMOS CLOCK DRIVER |
| 中文描述： | 1點(diǎn)15分PECL的低電壓的CMOS時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 127K |
| 代理商： | MPC949 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1996
10/96
The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15
outputs can be configured into a standard fanout buffer or into 1X and
1/2X combinations. The device features a low voltage PECL input, in
addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into
larger clock trees which utilize low skew PECL devices (see the
MC100LVE111 data sheet) in the lower branches of the tree. The fifteen
outputs were designed and optimized to drive 50
series or parallel
terminated transmission lines. With output to output skews of 300ps the
MPC949 is an ideal clock distribution chip for synchronous systems
which need a tight level of skew from a large number of outputs. For a
similar product with a smaller fanout and package consult the MPC946
data sheet.
Clock Distribution for Pentium
Systems with PCI
Low Voltage PECL Clock Input
2 Selectable LVCMOS/LVTTL Clock Inputs
350ps Maximum Output to Output Skew
Drives up to 30 Independent Clock Lines
Maximum Output Frequency of 150MHz
High Impedance Output Enable
52–Lead TQFP Packaging
3.3V VCC Supply
With an output impedance of approximately 7
, in both the HIGH and
the LOW logic states, the output buffers of the MPC949 are ideal for
driving series terminated transmission lines. More specifically each of the
15 MPC949 outputs can drive two series terminated transmission lines.
With this capability, the MPC949 has an effective fanout of 1:30 in
applications using point–to–point distribution schemes.
The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are
generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability
to allow the user to select the ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.
The MPC949 is fully 3.3V compatible. The 52 lead TQFP package was chosen to optimize performance, board space and cost
of the device. The 52–lead TQFP has a 10x10mm body size with a 0.65mm pin spacing.
Pentium is a trademark of Intel Corporation.
LOW VOLTAGE
1:15 PECL TO CMOS
CLOCK DRIVER
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D–03
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PDF描述 |
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| MPC950 | LOW VOLTAGE PLL CLOCK DRIVER |
| MPC951 | LOW VOLTAGE PLL CLOCK DRIVER |
| MPC952 | LOW VOLTAGE PLL CLOCK DRIVER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC949FA | 制造商:Motorola Inc 功能描述:FIFTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER, 52 Pin, Plastic, QFP |
| MPC950 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC950 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC951 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC951FA | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
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