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參數(shù)資料
| 型號： | MPC9456FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 312K |
| 代理商： | MPC9456FA |
MPC9456
Rev 3, 08/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
2.5 V and 3.3 V LVCMOS Clock
Fanout Buffer
The MPC9456 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer
designed for low-voltage mid-range to high-performance telecom, networking
and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are
supported for mixed-voltage applications. The MPC9456 offers 10 low-skew
outputs and a differential LVPECL clock input. The outputs are configurable and
support 1:1 and 1:2 output to input frequency ratios. The MPC9456 is specified
for the extended temperature range of –40 to 85
°C.
Features
Configurable 10 outputs LVCMOS clock distribution buffer
Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking and
computer applications
Supports high-performance differential clocking applications
Maximum output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
Tristable outputs
32-lead LQFP package
Ambient operating temperature range of –40 to 85
°C
32-lead Pb-free package available
Functional Description
The MPC9456 is a full static design supporting clock frequencies up to
250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks.
Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx
pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for
each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic
high state). Asserting MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive
terminated 50
transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.
Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of
the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a
7
×7mm2 32-lead LQFP package.
MPC9456
LOW VOLTAGE SINGLE OR DUAL
SUPPLY 2.5 V AND 3.3 V LVCMOS
CLOCK DISTRIBUTION BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC946 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:10 CMOS CLOCK DRIVER |
| MPC947 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:9 CLOCK DISTRIBUTION CHIP |
| MPC947FA | 制造商:Freescale Semiconductor 功能描述: |
| MPC948 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP |
| MPC948FA | 制造商:Motorola Inc 功能描述:TWELVE DISTRIBUTED-OUTPUT CLOCK DRIVER, 32 Pin, Plastic, QFP |
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