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參數(shù)資料
| 型號： | MPC941AE |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, LEAD FREE, LQFP-48 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 690K |
| 代理商： | MPC941AE |
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
MPC941
IDT / ICS CLOCK DISTRIBUTION CHIP
1
MPC941 REV. 8 APRIL 29, 2008
The MPC941 is a 1:27 low voltage clock distribution chip. The device features
the capability to select either a differential LVPECL or an LVCMOS compatible
input. The 27 outputs are LVCMOS compatible and feature the drive strength to
drive 50
series or parallel terminated transmission lines. With output-to-output
skews of 250 ps, the MPC941 is ideal as a clock distribution chip for the most
demanding of synchronous systems. For a similar product with a smaller number
of outputs, please consult the MPC940 data sheet.
LVPECL or LVCMOS Clock Input
250 ps Maximum Output-to-Output Skew
Drives Up to 54 Independent Clock Lines
Maximum Output Frequency of 250 MHz
High Impedance Output Enable
Extended Temperature Range: –40
°C to +85°C
48-Lead LQFP Packaging
48-Lead Pb-free Package Available
3.3 V or 2.5 V VCC Supply Voltage
With a low output impedance, in both the HIGH and LOW logic states, the
output buffers of the MPC941 are ideal for driving series terminated transmission
lines. More specifically, each of the 27 MPC941 outputs can drive two series
terminated 50
transmission lines. With this capability, the MPC941 has an
effective fanout of 1:54. With this level of fanout, the MPC941 provides enough
copies of low skew clocks for most high performance synchronous systems.
The differential LVPECL inputs of the MPC941 allow the device to interface
directly with an LVPECL fanout buffer like the MC100EP111 to build very wide
clock fanout trees or to couple to a high frequency clock source. The LVCMOS
input provides a more standard interface for applications requiring only a single
clock distribution chip at relatively low frequencies. In addition, the two clock
sources can be used as a test clock interface as well as the primary system clock.
A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock
input.
The MPC941 is fully 3.3 V and 2.5 V compatible. The 48-lead LQFP package was chosen to optimize performance, board
space and cost of the device. The 48-lead LQFP has a 7x7 mm body size.
LOW VOLTAGE 3.3 V/2.5 V
1:27 CLOCK
DISTRIBUTION CHIP
AE SUFFIX
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 932-03
SCALE 2:1
FA SUFFIX
48-LEAD LQFP PACKAGE
CASE 932-03
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