- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄2014 > MPC93R51AC (IDT, Integrated Device Technology Inc)IC PLL CLK DRIVER LV 32-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC93R51AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 13/13頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DRIVER LV 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類(lèi)型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)
MPC93R51 REVISION 4 JANUARY 31, 2013
9
2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Figure 6. VCCA Power Supply Filter
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
The MPC93R51 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R51 clock driver. For the series
terminated case, however, there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 7 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93R51 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 7. Single versus Dual Transmission Lines
The waveform plots in Figure 8 show the simulation results
of an output driving a single line versus two lines. In both
cases, the drive capability of the MPC93R51 output buffer is
more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93R51. The output
waveform in Figure 8 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36
series
resistor, plus the output impedance, does not match the
parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL =VS (Z0 (RS+R0 +Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 (18+17+25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
VCCA
VCC
MPC93R51
0.1
F
22 pF
0.1
F
RF
VCC
14
IN
MPC93R51
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC93R51
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9608AC | IC CLOCK BUFFER ZD 1:10 32-LQFP |
| MPC962309EJ-1H | IC BUFFER ZD 1:5 3.3V 16-TSSOP |
| MPC96877VK | IC CLK DRIVER 1:10 SDRAM 52-BGA |
| MPC9773AE | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| MPC9850VF | IC PLL CLOCK GENERATOR 100MAPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93R51ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93R51D | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC93R51FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 32LQFP - Tape and Reel |
| MPC93R52 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。