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參數(shù)資料
| 型號(hào)： | MPC9352FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 188K |
| 代理商： | MPC9352FAR2 |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9352/D
Rev 3, 06/2003
1
Motorola, Inc. 2003
3.3V/2.5V 1:11 LVCMOS Zero
Delay Clock Generator
The MPC9352 is a 3.3V or 2.5V compatible, 1:11 PLL based clock
generator targeted for high performance clock tree applications. With
output frequencies up to 200 MHz and output skews lower than 200 ps
the device meets the needs of most demanding clock applications.
Features
Configurable 11 outputs LVCMOS PLL clock generator
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 200 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3B2,
2
B3, 1B3 and 1B2
2.5V and 3.3V LVCMOS compatible
Maximum output skew of 200 ps
Supports zero–delay applications
Designed for high–performance telecom, networking and computing
applications
32 lead LQFP package
Ambient Temperature Range –40°C to +85°C
Functional Description
The MPC9352 is a fully 3.3V or 2.5V compatible PLL clock generator
and clock driver. The device has the capability to generate output clock
signals of 16.67 to 200 MHz from external clock sources. The internal PLL
optimized for its frequency range and does not require external look filter
components. One output of the MPC9352 has to be connected to the PLL
feedback input FB_IN to close the external PLL feedback path. The
output divider of this output setting determines the PLL frequency
multiplication factor. This multiplication factor, F_RANGE and the
reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be
configured individually for all three output banks by the FSELx pins
supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC9352 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC9352 is package in a 32 ld LQFP.
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
MPC9352
LOW VOLTAGE
3.3V/2.5V LVCMOS 1:11
CLOCK GENERATOR
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