參數資料
型號: MPC9352AC
廠商: IDT, Integrated Device Technology Inc
文件頁數: 10/16頁
文件大?。?/td> 0K
描述: IC CLK GEN ZD 1:11 32-LQFP
標準包裝: 250
類型: PLL 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS
輸出: LVCMOS
電路數: 1
比率 - 輸入:輸出: 1:11
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應商設備封裝: 32-TQFP(7x7)
包裝: 托盤
MPC9352 REVISION 8 JANUARY 31, 2013
3
2013 Integrated Device Technology, Inc.
MPC9353 Data Sheet
3.3V/2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
F_RANGE
Input
LVCMOS
PLL frequency range select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0–4, QB0–3, QC0–1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin VCCA. Please
see Applications Information section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2. Function Table
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 9 and Table 10 for supported frequency ranges and output to input frequency ratios.
F_RANGE
0
VCO
1 (High input frequency range)
VCO
2 (Low input frequency range)
FSELA
0
Output divider
4
Output divider
6
FSELB
0
Output divider
4
Output divider
2
FSELC
0
Output divider
2
Output divider
4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset, the PLL feedback loop is
open and the VCO is operating at its lowest frequency.
The MPC9352 requires reset at power-up and after
any loss of PLL lock. Loss of PLL lock may occur when
the external feedback path is interrupted. The length of
the reset pulse should be greater than two reference
clock cycles (CCLK).
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is substituted for
the internal VCO output. MPC9352 is fully static and
no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
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