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參數(shù)資料
| 型號(hào)： | MPC92474FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | MPC92474FA |
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC92474
PREL
IM
IN
AR
Y
S_LOAD pin after the shift register is fully loaded will transfer
the divide values into the counters. The HIGH-to-LOW
transition on the S_LOAD input will latch the new divide
values into the counters. Figure 3 illustrates the timing
diagram for both a parallel and a serial load of the MPC92474
synthesizer. M[8:0], NA[2:0] and NB[2:0] are normally
specified once at power-up through the parallel interface, and
then possibly again through the serial interface. This
approach allows the application to come up at one frequency
and then change or fine-tune the clock as the ability to control
the serial interface becomes available.
Using the Test and Diagnosis Output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[1:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the CMOS output is not able to toggle
fast enough for higher output frequencies and should only be
used for test and diagnosis. The T1 and T0 control bits are
preset to ‘00' when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter-free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter of
the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin. Most of the signals
available on the TEST output pin are useful only for
performance verification of the MPC92474 itself.
Figure 3. Serial Interface Timing Diagram
Table 8. Test and Debug Configuration for TEST
T[1:0]
TEST Output
T1
T0
0
Logic 0
0
1
S Data Shift Register Output
1
0
M Counter out
1
LVCMOS FOUTA0
S_CLOCK
S_DATA
S_LOAD
M[8:0]
N[1:0]
P_LOAD
NB11 NB0 NA2 NA1 NA0 M8
M7
M6
M5
M4
M3
M2 M1
M0
M, N
First
Bit
Last
Bit
T0
T1
NB2
SS1
SS2
SS0
SS3
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