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參數(shù)資料
| 型號(hào)： | MPC92429FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 400 MHz Low Voltage PECL Clock Synthesizer |
| 中文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 216K |
| 代理商： | MPC92429FN |
MPC92429
TIMING SOLUTIONS
7
MOTOROLA
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Table 8. Output Frequency Range for f
XTAL
= 16 MHz
N
F
1
0
Value
F
range
OUT
F
step
OUT
OUT
0
0
1
M
200 - 400 MHz
1 MHz
0
1
2
M
÷
2
100 - 200 MHz
500 kHz
1
0
4
M
÷
4
50 - 100 MHz
250 kHz
1
1
8
M
÷
8
25 - 50 MHz
125 kHz
Example frequency calculation for an 16 MHz input
frequency
Ifan outputfrequency of131 MHz was desired the following
steps would be taken to identify the appropriate M and N
values. According to Table 8, 131 MHz falls in the frequency
set by an value of 2 so N[1:0] = 01. For N = 2 the output
frequency is F
OUT
= M
÷
2 and M = F
OUT
x 2. Therefore M =
2 x 131 = 262, so M[8:0] = 100000110. Following this
procedure a usercan generate any whole frequency between
25 MHz and 400 MHz. Note than for N > 2 fractional values of
can be realized. The size of the programmable frequency
steps (and thus the indicator of the fractional output
frequencies achievable) will be equal to:
f
STEP
= f
XTAL
÷
16
÷
N
(5)
Using the parallel and serial interface
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOADsignalsuch thata LOWto HIGHtransitionwill
latch the information present on the M[8:0] and N[1:0] inputs
into the M and N counters. When the P_LOAD signal is LOW
the input latches will be transparent and any changes on the
M[8:0] and N[1:0] inputs will affect the FOUT output pair. To
use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the nexttwo and the
M register with the final eight bits of the data stream on the
S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8).A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
intothecounters.TheHIGHtoLOWtransitionon theS_LOAD
input will latch the new divide values into the counters. Figure
4 illustrates the timing diagram for both a parallel and a serial
load of the MPC92429 synthesizer. M[8:0] and N[1:0] are
normally specified once at power–up through the parallel
interface,and then possibly again through the serialinterface.
This approach allows the application to come up at one
frequencyandthenchangeorfine–tunetheclockastheability
to control the serial interface becomes available.
Using the test and diagnosis output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream.Itis notconfigurable through the parallel
interface. Although it is possible to select the node that
represents F
OUT
, the CMOS output is not able to toggle fast
enoughfor higheroutputfrequenciesandshouldonlybeused
for test and diagnosis. The T2, T1 and T0 control bits are
presetto ‘000’when P_LOADis LOWso thatthe PECL FOUT
outputs are as jitter–free as possible. Any active signal on the
TEST outputpin willhave detrimentalaffectson thejitterofthe
PECLoutputpair.Innormaloperations,jitterspecificationsare
only guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functionsforthispin.MostofthesignalsavailableontheTEST
output pin are useful only for performance verification of the
MPC92429 itself. However the PLL bypass mode may be of
interest at the board level for functional debug. When T[2:0] is
setto110theMPC92429isplacedinPLLbypassmode.Inthis
mode the S_CLOCK input is fed directly into the M and N
dividers.The Ndividerdrives the F
OUT
differentialpairand the
M counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving F
OUT
directly gives the user more control on the test clocks sent
through the clock tree. Figure 6 shows the functional setup of
the PLL bypass mode. Because the S_CLOCK is a CMOS
leveltheinputfrequency islimited to200 MHz.This meansthe
fastest the F
OUT
pin can be toggled via the S_CLOCK is 100
MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1).
Note that the M counter output on the TEST output will not be
a 50% duty cycle.
Table 9. Test and Debug Configuration for TEST
T[2:0]
TEST output
T2
T1
T0
0
0
0
14-bit shift register out
a
0
0
1
Logic 1
0
1
0
f
XTAL
÷
16
M-Counter out
0
1
1
1
0
0
FOUT
1
0
1
Logic 0
1
1
0
M-Counter out in PLL-bypass mode
1
1
1
FOUT
÷
4
a. Clocked out at the rate of S_CLOCK
Table 10. Debug Configuration for PLL bypass
a
Output
Configuration
F
OUT
TEST
S_CLOCK
÷
N
M-Counter out
b
a. T[2:0]=110. AC specifications do not apply in PLL bypass
mode
b. clocked out at the rate of S_CLOCK
÷
(4
N)
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